The Effect of Placement on Yield for Standard Cell Designs

The ability to improve the yield of integrated circuits through layout modi cation has been r ecognize d and several techniques for yield enhanced routing and compaction have been developed. Yield improvement during routing is however, limited by the predetermined placement. It is conc eivable ther efor e, that di er ent placements of the modules (e.g., standard or custom cells) may lead to very di er ent yieldenhanced routings withdi er ent projectedyields. This is conceptually similar to the e ect that the oorplanning of the entir e chip has on the yield [2], but while chip oorplanning deals with the major building blocks, plac ementdeals with the modules within an individual block. Yield enhanced plac ementof modules has not been attempted before mainly due to the diÆculty of estimating the yield of the block b efor e the r outing is done.R ecently, a te chnique for estimating the yield prior to the routing has been developed [1] making it possible to modify the placement in order to achieve higher yield. The goals of this paper are to investigate the e ect that placement has on the projected yield and to modify a standard cell placement algorithm so that yield becomes a design obje ctive.